ArticleAuthors: FUTATSUGI, Kokich (2006)
Verifying specifications is still one of the most important undeveloped reseach
topics in software engineering. It is important because quite a few critical bugs are
caused at the level of domains, requirements, and/or designs. It is also important for
the cases where no program codes are generated and specifications are analyzed and
verified only for justifying models of problems in real world.
Formal methods is not the “silver bullet”, but is still expected to improve the
practice of constructions/analyses/verifications of domain/requirement/design speci-
fications. 
